Multi Option Question Page 1230

<<= Back Next =>>

You Are On Multi Choice Question Bank SET 1230

61501. A very critical dimension in project management is the time your boss will give you to complete the HDL project.

61502. In the keypad HDL encoder, the data signal is used to combine the row and column encoder data to make a 4-bit value representing the key that was pressed.

61503. One CASE construct inside another CASE construct is called a do-loop.

61504. A frequency counter is a circuit that can measure and display the frequency of a signal.

61505. In the digital clock project, a MOD-60 BCD counter is made from a MOD-10 counter cascaded to a MOD-6 BCD counter.

61506. The full-step sequence always has two coils of the stepper motor energized in any state of the sequence and typically causes 30° of shaft rotation per step.

61507. The direct drive mode of a stepper motor allows for less control by the operator.

61508. In the frequency counter, a pulse shaper block is needed to ensure that the unknown signal, whose frequency is to be measured, will be compatible with the clock input for the counter block.

61509. In the digital clock project, the AHDL block codes are connected using graphic design files.

61510. In HDL, one of the strategies used in strategic planning is to find the speed requirements.

61511. In the keypad HDL encoder, the ts bit array represents a tristate buffer.

61512. In the VHDL code of the stepper motor, the cout outputs are bit_vector type because they are binary bit patterns.

61513. In the keypad HDL encoder, as long as all columns are high the ring counter is enabled and counting.

61514. In the frequency counter, the pulse width of the enable signal is very critical for taking an accurate frequency measurement.

61515. One of the first steps in any HDL project is to define its scope by naming each input and output.

61516. The wave-drive sequence of a stepper motor has more torque and operates more smoothly than the full-step sequence at moderate speeds.

61517. In the digital clock project, the ENT input and RCO output can be used for synchronous counter cascading.

61518. In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce sine wave pulses at the rate of 60 pps.

61519. In the digital clock project HDL, the 1 pps signal is used as a synchronous clock for all of the counters' stages, which are synchronously cascaded.

61520. In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the edge trigger clock moves the display to 12:00:00.

61521. In the keypad HDL encoder, after releasing a key the ring counter resumes its counting sequence.

61522. In the keypad HDL encoder, the freeze bit detects when a key is released.

61523. In HDL when a circuit is simulated on a computer, the designer must create all the different scenarios that will be experienced by the actual circuit and must also know the proper response to those inputs.

61524. In the keypad HDL encoder, NANDing of the columns is used to activate the freeze bit.

61525. In the digital clock project, the 1 pps signal is used as a synchronous clock for all of the counter stages, which are ________.

61526. In the keypad encoder, the ________ must hold in its current state until a key is released.

61527. The interface of the stepper motor needs to operate in one of ________ mode(s).

61528. In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce square pulses at the rate of ________.

61529. A frequency counter ________ a signal.

61530. When coming up with a strategy for dividing the overall project into manageable-size pieces one must ________.

61531. VARIABLES are considered to be updated within a sequence of statements in a PROCESS, whereas SIGNALS referred to in a PROCESS are updated when the PROCESS .

61532. The major blocks of the frequency counter are the counter, ________, decoder/display, and the timing and control unit.

61533. In the keypad encoder, just after the 4 ms mark, the simulation initiates the release of the key by changing the column value to ________, which causes the d output to go into its Hi-Z state.

61534. One aspect of project planning and management is the selection of ________ that will best fit the application.

61535. In the keypad encoder, the ring counter is implemented using ________ that responds to the clk input.

61536. In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the enable input is active. On the next clock pulse the AM/PM flip-flop will ________.

61537. In the frequency counter, the control clock is derived from the ________ by frequency dividers controlled in the control and timing block.

61538. Using one case construct inside another is known as ________.

61539. In the frequency counter, the length of time for the ________ to be enabled can be selected with the range select input.

61540. In the digital clock project HDL code, the MOD-12 counter is using ________.

61541. Each ________, starting at the simplest level, should be built in HDL.

61542. In the keypad encoder, the ________ activate(s) the freeze bit only when one column is low.

61543. In a real project, the first step of definition often involves some ________ on the part of the project manager.

61544. One of the first steps in small-project management is to determine ________.

61545. The timing and control block provides the ________ for the frequency counter.

61546. The stepper motor HDL will ignore its counter inputs and pass control inputs directly to the output when set in mode ________.

61547. The full-step sequence of a stepper motor always has two coils energized in any state of the sequence and typically causes ________ of shaft rotation per step.

61548. Depending on the ________ the IC is in, the output of the stepper motor HDL will respond to each pulse by changing state.

61549. The step rate of the simulation of a stepper motor is probably ________ the actual stepper motor.

61550. A very critical dimension in project management is ________.

<<= Back Next =>> Terms And Service:We do not guarantee the accuracy of available data ..We Provide Information On Public Data.. Please consult an expert before using this data for commercial or personal use

61501. A very critical dimension in project management is the time your boss will give you to complete the HDL project. (adsbygoogle = window.adsbygoogle || []).push({});