61451. The flash converter is the fastest analog-to-digital conversion method.
61452. The ADC0804 is an example of a successive-approximation ADC.
61453. Incorrect codes are a form of output error for a DAC.
61454. In a binary-weighted-input digital-to-analog converter, the values of the input resistors are chosen to be proportional to the binary weights of the corresponding input bits.
61455. An offset error in a DAC will show up as an incorrect analog output ________.
61456. An ADC that compares each bit, one at a time, with the input analog signal is a ________.
61457. A standard logic device can be connected on a bus system as an open-collector logic device by connecting each output to a ________.
61458. A monotonicity error in a DAC will show up as an incorrect analog output ________.
61459. Of the methods listed, the fastest A/D conversion is done by a ________.
61460. The principal advantage of the three-wire handshake on the GPIB is that it ________.
61461. An ADC that uses an up/down counter (and other devices) to follow changes in the input analog signal is a ________.
61462. The number of data lines on the GPIB is ________.
61463. The resolution of a DAC can be expressed as the ________.
61464. Assume that in a certain 4-bit weighted ladder DAC, the input representing the most significant bit is applied to a 20 k resistor. What is the size of the resistor that represents the least significant bit?
61465. In a flash analog-to-digital converter, the output of each comparator is connected to an input of a ________.
61466. Which term applies to the maintaining of a given signal level until the next sampling?
61467. An op-amp has very ________.
61468. For a 4-bit DAC, the least significant bit (LSB) is ________.
61469. The dual-slope analog-to-digital converter finds extensive use in ________.
61470. In the keypad application, what does the data signal define?
61471. What does the ring counter in the HDL keypad application do when a key is pressed?
61472. In the digital clock project, the purpose of the frequency prescaler is to:
61473. Which is not a step that should be followed in project management?
61474. In the keypad application, what does the preset state of the ring counter define?
61475. In an HDL stepper motor design, why is there more than one mode?
61476. Which is not a major block of an HDL frequency counter?
61477. In a full-step sequence involving two flip-flops driving four coils of a stepper motor, how far will the stepper motor step?
61478. Which is not a step used to define the scope of an HDL project?
61479. In the digital clock project, what is the frequency of the MOD-6 counter in the minutes section?
61480. Why should a real hardware functional test be performed on the HDL stepper motor design?
61481. What does the major block of an HDL code emulation of a keypad include?
61482. The accuracy of the frequency counter depends on the:
61483. In the frequency counter, if the clock generator produces a 100 kHz system clock signal, how many decade counters are required to measure 1 Hz?
61484. What must a stepper motor HDL application include?
61485. Which is not a step in strategic planning for HDL development?
61486. In the frequency counter, when is the new count stored in the display register?
61487. What are two ways to remember the current state of a counter in VHDL?
61488. In the digital clock project, what type of counter is used to count to 59 seconds?
61489. In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and dav is LOW, what is the status of the d outputs?
61490. In the frequency counter, what is the function of the Schmitt trigger circuit?
61491. List three basic blocks in the digital clock project.
61492. When designing an HDL digital system, which is the worst mistake one can make?
61493. In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the d output to go into its Hi-Z state. On the next rising clock edge, what happens to dav?
61494. For the frequency counter, which is not a control signal from the control and timing block?
61495. Top-down design means that we start at the highest level of the hierarchy, or that the entire project is considered to exist in a closed dark box with inputs and outputs.
61496. The frequency counter measures frequency by enabling a counter to count the number of pulses of the incoming waveform during a precisely specified period of time called the sampling time.
61497. In the digital clock project, frequency prescaling is used to take a 1 pps input and transform it into a 60 pps timing signal.
61498. The half-step sequence of a stepper motor is created by inserting a start with only one coil energized between full steps.
61499. One of the first steps in any HDL project is to define its scope by knowing the nature of all the signals that are interconnected to pieces of the project.
61500. In HDL, one of the strategies used in strategic planning is to find a way to test each piece of the project.
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