70652. The resolution of 4 bit counting ADC is 0.5 volt, for an Analog input of 6.6 volts. The digital output of ADC will be
70653. 9's complement of 1210 is
70654. The minterm designation for ABCD is
70655. Read the following statements The circuitry of ripple counter is more complex than that of synchronous counter.The maximum frequency of operation of ripple counter depends on the modulus of the counter.The maximum frequency of operation of synchronous counter does not depend on the modulus of the counter. Which of the above statements are correct?
70656. The role of the payment gateway is
70657. A multiple emitter transistor has many emitters and collectors.
70658. A mode-10 counter can divide the clock frequency by a factor of
70659. Which of the following binary numbers is equivalent to decimal 10?
70660. A 4 bit synchronous counter has flip flops having propagation delay of 50 ns each and AND gates having propagation delay of 20 ns each. The maximum frequency of clock pulses can be
70661. A counter has 4 flip flops. It divides the input frequency by
70662. A pulse train with a 1 MHz frequency is counted using a 1024 modulus ripple counter using JK flip flops. The maximum propagation delay for each flip-flop should be
70663. What will be maximum input that can be converted for a 6 bit dual slope A/D converter uses a reference of -6v and a 1 MHz clock. It uses a fixed count of 40 (101000).
70664. In the given figure shows a logic circuit. The minimum Boolean expression for this circuit is
70665. If number of information bits is 11, the number of parity bits in Hamming code is
70666. The number of digit 1 present in the binary representation of 3 x 512 + 7 x 64 + 5 x 8 + 3 is
70667. Out of 5 M x 8, 1 M x 16, 2 M x 16 and 3M x 8 memories, which memory can store more bits?
70668. A 6 bit ladder A/D converter has input 101001. The output is (assume 0 = 0 V and 1 = 10 V)
70669. A ripple counter has 4 bits and uses flip flops with propagation delay time of 25 ns. The maximum possible time for change of state will be
70670. A counter has a modulus of 10. The number of flip flops is
70671. The counter shown in the given figure is built using 4 -ve edge triggered toggle FFs. The FF can be set asynchronously when R = 0. The combinational logic required to realize a modulo-13 counter is
70672. In the figure, the LED
70673. A 4 bit ripple counter uses flip flops with propagation delay of 50 ns each. The maximum clock frequency which can be used is
70674. An AND gate has two inputs A and B and one inhibit input S. Out of total 8 input states, output is 1 in
70675. 26810 = __________ .
70676. In a JK Master slave flip flop
70677. The counter which require maximum number of FF for a given mod counter is
70678. Four inputs A, B, C, D are fed to a NOR gate. The output of NOR gate is fed to an inverter. The output of inverter is
70679. The content of which of the following determines the state of the CPU at the end of the execute cycle (when the interrupt is recognized)? Program counterProcessor registerCertain status conditions Select the correct answer using the codes given below :
70680. In a gate output is Low if and only if all inputs are High. The gate is
70681. With on-chip decoding, n address lines can access
70682. The circuit in the figure is has two CMOS-NOR gates. This circuit functions as a
70683. A 6 bit DAC uses binary weighted resistors. If MSB resistor is 20 k ohm, the value of LSB resistor is
70684. A 6 bit dual slope A/D converter uses a reference of -6v and a 1 MHz clock. It uses a fixed count of 40 (101000). Then, what will be input, if the output register shows 100111 at the end of conversion.
70685. In the TTL circuit in the figure, S2 to S0 are select lines and X7 to X0 are input lines. S0 and X0 are LSBs. The output Y is
70686. The number of accumulators in 6800 are
70687. If an analog voltage is expressed in binary using 4 bits, each successive binary count would represent
70688. In a 4 input AND gate, the total number of High outputs for 16 input states are
70689. Symmetrical square wave of time period 100 μs can be obtained from square wave of time period 10 μs by using
70690. The Boolean expression for the shaded area in the Venn diagram is
70691. The initial state of a Mod-16 counter is 0110. After 37 clock pulses the state of counter will be
70692. A 14 pin AND gate IC has __________ AND gates.
70693. In 8085 microprocessor, how many lines are there in data bus?
70694. The basic shift register operations are
70695. The hexadecimal number 'A0' has the decimal value
70696. The logic realized by the circuit shown in figure below is
70697. A 4 bit ripple counter is in 0000 state. The clock pulses are applied and then removed. The counter reads 0011. The number of clock pulses which have occurred are
70698. TTL logic is preferred to DRL logic because
70699. Assertion (A): Schottky transistors are preferred over normal transistors in digital circuits Reason (R): A Schottky transistor when used as a switch, between cutoff and active region.
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