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You Are On Multi Choice Question Bank SET 1223
61151. When multiplying 13 × 11 in binary, what is the third partial product?
(A): 1011 (B): 00000000 (C): 100000 (D): 100001
61152. How many BCD adders would be required to add the numbers 97310 + 3910?
(A): 3 (B): 4 (C): 5 (D): 6
61153. The selector inputs to an arithmetic/logic unit (ALU) determine the:
(A): selection of the IC (B): arithmetic or logic function (C): data word selection (D): clock frequency to be used
61154. What is wrong, if anything, with the circuit in the given figure based on the logic analyzer display accompanying the circuit?
(A): The CO terminal is shorted to ground. (B): The S1 output is shorted to Vcc. (C): The P1 input is not being added into the total. (D): Nothing is wrong; the circuit is functioning correctly.
61155. Which of the statements below best describes the given figure?
(A): Half-carry adder; Sum = 0, Carry = 1 (B): Half-carry adder; Sum = 1, Carry = 0 (C): Full-carry adder; Sum = 1, Carry = 0 (D): Full-carry adder; Sum = 1, Carry = 1
61156. An 8-bit register may provide storage for two's-complement codes within which decimal range?
(A): +128 to –128 (B): –128 to +127 (C): +128 to –127 (D): +127 to –127
61157. A full-adder adds ________.
(A): two single bits and one carry bit (B): two 2-bit binary numbers (C): two 4-bit binary numbers (D): two 2-bit numbers and one carry bit
61158. The carry propagation delay in 4-bit full-adder circuits:
(A): is cumulative for each stage and limits the speed at which arithmetic operations are performed (B): is normally not a consideration because the delays are usually in the nanosecond range (C): decreases in direct ratio to the total number of full-adder stages (D): increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations
61159. An input to the mode pin of an arithmetic/logic unit (ALU) determines if the function will be:
(A): arithmetic or logic (B): positive or negative (C): with or without carry
61160. Could the sum output of a full-adder be used as a two-bit parity generator?
(A): Yes (B): No
61161. In VHDL, what is a GENERATE statement?
(A): The start statement of a program (B): Not used in VHDL or ADHL (C): A way to get the computer to generate a program from a circuit diagram (D): A way to tell the compiler to replicate several components
61162. Binary subtraction of a decimal 15 from 43 will utilize which two's complement?
(A): 101011 (B): 110000 (C): 011100 (D): 110001
61163. Which of the following is the primary advantage of using binary-coded decimal (BCD) instead of straight binary coding?
(A): Fewer bits are required to represent a decimal number with the BCD code. (B): BCD codes are easily converted from decimal. (C): the relative ease of converting to and from decimal (D): BCD codes are easily converted to straight binary codes.
61164. The contributors of Co-operative idea in England by Robert Owen and:
(A): Raiffeisen (B): William king (C): Schulze (D): None of these
61165. Convert each of the decimal numbers to two's-complement form and perform the addition in binary. +13 –10 add –7 add +15
(A): 0001010000000101 (B): 0000011000011001 (C): 0000011000000101 (D): 1111011011110101
61166. Add the following binary numbers. 0010 0110   0011 1011   0011 1100 +0101 0101   +0001 1110   +0001 1111
(A): 0111 10110100000101011011 (B): 0111 10110101100101011011 (C): 0111 01110101100101011011 (D): 0111 01110100000101011011
61167. The carry propagation delay in full-adder circuits:
(A): is normally not a consideration because the delays are usually in the nanosecond range. (B): decreases in a direct ratio to the total number of FA stages. (C): is cumulative for each stage and limits the speed at which arithmetic operations are performed. (D): increases in a direct ratio to the total number of FA stages but is not a factor in limiting the speed of arithmetic operations.
61168. What is the difference between a full-adder and a half-adder?
(A): Half-adder has a carry-in. (B): Full-adder has a carry-in. (C): Half-adder does not have a carry-out. (D): Full-adder does not have a carry-out.
61169. The summing outputs of a half- or full-adder are designated by which Greek symbol?
(A): omega (B): theta (C): lambda (D): sigma
61170. Subtract the following hexadecimal numbers. 47   34   FA –25   –1C   –2F
(A): 2218CB (B): 2217CB (C): 2219CB (D): 2218CC
61171. What is the correct output of the adder in the given figure, with the outputs in the order:
(A): 10111 (B): 11101 (C): 01101 (D): 10011
61172. The management of joint Stock Company is:
(A): Board of directorate (B): Committee (C): Chairman (D): None of these
61173. The BCD addition of 910 and 710 will give initial code groups of 1001 + 0111. Addition of these groups generates a carry to the next higher position. The correct solution to this problem would be to:
(A): ignore the lowest order code group because 0000 is a valid code group and prefix the carry with three zeros (B): add 0110 to both code groups to validate the carry from the lowest order code group (C): disregard the carry and add 0110 to the lowest order code group (D): add 0110 to the lowest order code group because a carry was generated and then prefix the carry with three zeros
61174. Subtract the following binary numbers. 0101 1000   1010 0011   1101 1110 –0010 0011   –0011 1000   –0101 0111
(A): 001101000110101010000110 (B): 001101010110101110000111 (C): 001101010110101010000111 (D): 001101010110101010000110
61175. Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?
(A): to decrease the cost (B): to make it smaller (C): to slow down the circuit (D): to speed up the circuit
61176. Find the 2's complement of –1101102.
(A): 1101002 (B): 1010102 (C): 0010012 (D): 0010102
61177. What logic function is the sum output of a half-adder?
(A): AND (B): exclusive-OR (C): exclusive-NOR (D): NAND
61178. The binary adder circuit is designed to add ________ binary numbers at the same time.
(A): 2 (B): 4 (C): 6 (D): 8
61179. An ALU is a multipurpose device capable of providing several different logic operations.
(A): True (B): False
61180. BCD arithmetic is performed using base 10 numbers.
(A): True (B): False
61181. A full adder has a carry-in.
(A): True (B): False
61182. Hexadecimal is a base 4 numbering system.
(A): True (B): False
61183. The solution to the binary problem 00110110 – 00011111 is 00011000.
(A): True (B): False
61184. A binary sum is made up of only 1s and 0s.
(A): True (B): False
61185. Overflow indicators in ALU circuits indicate when add or subtract operations produce results that are too large to fit into four bits.
(A): True (B): False
61186. The inputs of a full adder are labeled A1, B1, and Cin.
(A): True (B): False
61187. Larger number capacities may be obtained from 2-bit adders by paralleling them.
(A): True (B): False
61188. If [A] = 10 and [B] = 01, then [A] + [B] = [ ].
(A): True (B): False
61189. 111010002 is the 2's-complement representation of –24.
(A): True (B): False
61190. The look-ahead-carry adder is slower than the ripple-carry adder because it requires additional logic circuits.
(A): True (B): False
61191. The solution to the binary problem 1011 × 0110 is 01100110.
(A): True (B): False
61192. The solution to the BCD problem 0101 + 0100 is 00001001BCD.
(A): True (B): False
61193. A macrofunction is a self-contained description of a logic circuit with all of its inputs, outputs, and operational characteristics defined.
(A): True (B): False
61194. A half-adder circuit would normally be used each time a carry input is required in an adder circuit.
(A): True (B): False
61195. The binary subtraction 0 – 1 = isdifference = 1borrow = 0
(A): True (B): False
61196. A sign bit of "1" in the difference of a 2's-complement subtraction problem indicates the magnitude is negative and in true binary form.
(A): True (B): False
61197. Constants must be included in a package.
(A): True (B): False
61198. 10011100 in two's-complement notation has a decimal value of –100.
(A): True (B): False
61199. There are four possible combinations for subtracting two binary numbers.
(A): True (B): False
61200. It is not necessary to have the same number of bits when adding or subtracting signed binary numbers in the 2's-complement system.
(A): True (B): False
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