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1. The carry propagation delay in 4-bit full-adder circuits:
(A): is cumulative for each stage and limits the speed at which arithmetic operations are performed
(B): is normally not a consideration because the delays are usually in the nanosecond range
(C): decreases in direct ratio to the total number of full-adder stages
(D): increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations
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