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Multiple Choice Questions
1. In a D latch
(A): data bit D is fed to S input and D to R input
(B): data bit D is fed to R input and D to S input
(C): data bit D is fed to both R and S inputs
(D): data bit D is not fed to any input
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MCQ->If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.....
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