61201. Full adder results are typically stored in registers.
61202. The representation of –110 in eight-bit two's-complement notation is 11110111.
61203. Binary division and decimal division use the same procedure.
61204. When the 2's-complement system is used, the number to be subtracted is changed to its 2's complement and then added to the minuend.
61205. Full adders can add two numbers and need not have a carry input or a carry output.
61206. The VHDL compiler requires libraries to be specified at the beginning of the code if components from those libraries are being used.
61207. The carry-out of a binary adder is identified using the summation symbol, sigma.
61208. The 74LS382 ALU is a 24-pin arithmetic/logic unit.
61209. The two's-complement method is used in computer systems that perform arithmetic.
61210. Digital computers use an easier method to subtract binary numbers, called one's complement.
61211. Binary multiplication is like decimal multiplication except you deal only with 1s and 0s.
61212. The solution to the binary problem 1011 – 0111 is 1000.
61213. A 74HC283 can be used to implement a 4-bit full adder.
61214. The range of negative numbers when using an eight-bit two's-complement system is –1 to –128.
61215. If no bits are designated inside square braces, [ ], it means the variable is the null set.
61216. This logic gate is used to produce an arithmetic sum XOR.
61217. The solution to the binary problem 0101 + 1111 is 10100.
61218. ALU circuits cannot be cascaded to perform functions on more than four bits.
61219. In VHDL, the architecture declaration always begins with the ________ of variable signals or components that will be used in the concurrent description between BEGIN and END.
61220. When decimal numbers with several digits are to be added together using BCD adders ________.
61221. The binary adder circuit is designed to add ________ binary number(s) at a time.
61222. The 74HC382 ALU can perform ________ operations.
61223. Subtraction of the 2's-complement system actually involves the operation of ________.
61224. FC48 – AB91 = ________.
61225. In BCD addition, the value ________ is added to any invalid code group.
61226. In AHDL macrofunctions, the first thing that should go into any source file is ________ your code.
61227. The circuit shown is a(n) ________.
61228. The binary addition of 1 + 1 = ________.
61229. A 74HC283 can be used to implement a(n) ________ adder.
61230. The two's complement of 00001111 is ________.
61231. Inside a computer all arithmetic operations take place in the ________.
61232. –910 represented in eight-bit two's-complement notation is ________.
61233. Solve this binary problem: 01011000 ÷ 00001011 = ________.
61234. If [A] = 10 and [B] = 01, then [A] [b] = ________.
61235. Binary numbers can be added together in a basic parallel-adder circuit when ________.
61236. To make an eight-bit adder from two four-bit adders you must connect ________.
61237. Packages are used to contain ________ and other information that must be available to all entities in the design file.
61238. 34FC + AD31 = ________.
61239. Solve this binary problem: 1001 × 1100 = ________.
61240. A four-bit adder can perform ________.
61241. The concurrent section of the hardware description is where the ________ are interconnected.
61242. The contents of the A register after is ________.
61243. The binary subtraction 1 – 1 = ________.
61244. When subtracting 6 from 9 using 2's-complement methods, the ________ is 2's complemented before the addition.
61245. When performing binary addition using the 2's-complement method, an ________ can occur if ________ are of the same ________; the error is indicated by a(n) ________.
61246. Negation is performed by simply performing the ________ operation.
61247. Solve this BCD problem: 0101 + 0110 = ________.
61248. For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is:
61249. What is the first thing you will need if you are going to use a macrofunction?
61250. Perform subtraction on each of the following binary numbers by taking the two's-complement of the number being subtracted and then adding it to the first number.01001011000001100111
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